A microprocessor of the kind, for example, which are used in automotive engine controls and a wide variety of other applications is capable of carrying many control functions at the same time by interleaving the operations of the various functions. Generally the microprocessor has to receive signals representing time events, and respond to the signals by outputting other signals, also often critically timed to control engine functions such as spark timing and fuel injection. Such microprocessors may employ a timer processor unit (TPU) which has several channels individually programmed to deal with the various timed signals.
Such a timer processor operates independently of but under the control of a central processor unit (CPU) and must, among other functions, be able to provide time data to the CPU. Both the CPU and the TPU are driven by a system clock which operates at megahertz rates to rapidly step each unit through its program functions. A random access memory (RAM) in the TPU is accessible by the CPU so that time data is obtained by addressing registers in the RAM where the TPU has placed the relevant information. The microprocessor architecture defines the registers of a uniform size, for example 16 bits. One or more timers in the TPU is used to regulate the various channels.
For each timer, one of the registers is driven by the system clock to serve as a free-running counter, called a hardware timer, which rapidly accumulates counts up to its limit and then rolls over to a clear state and continues counting, repeating this process continuously. At any moment the timer value can be stored to another register for reading by the CPU or for use by other TPU functions. A limitation of the timer is that it has only the size of the register so that special manipulations are required to manage larger counts. The availability of a larger count is desirable to provide a larger time range or to accommodate faster clock rates for better timer resolution.
It is proposed to control a second register through microcode software in the TPU to increment each time the hardware timer (first register) rolls over to its clear state. Then an extended timer value is achieved by concatenating the values in the second register and the hardware counter. Either the CPU or the TPU can get the extended timer value by reading the two registers. In practice, there can be a delay between the rollover of the first register and the incrementing of the second register. This leads to a short time when the registers are non-coherent, i.e., the first register has been cleared and the second register does not yet indicate that event, so that the combination of the two values in that period would yield an erroneous result.